Re: How VLSI systems deal with interferences?

VERY good question!!!  Thousands of people have been working on this for 
many years, and only partial solutions have been developed:
1:  Eliminate interference in the first place, by layout techniques or by 
slowing the clock edges down.  This last slows the circuit down, so is 
undesirable.
2.  PC layout:  minimizing the length of chip/board traces, so as not to 
radiate interference and to minimize the susceptibility of the trace to 
interference.  Also route the trace over a 'ground plane', which 
minimizes radiation/susceptibility, at the cost of increased chip area.
3.  Route noisy traces, such as clock lines, away from susceptible traces 
such as input nodes.  Also put "guard" traces, connected to ground, 
between radiating circuits/traces and susceptible circuitry.
4.  Place noisy circuitry, such as clock oscillators, away from 
susceptible circuitry such as analog or phase-locked loops.  This costs 
chip area.
5.  Use controlled source and load impedances on all lines to minimize 
standing waves and thus radiation.  This costs power and is often an 
unacceptable burden.
6.  Use differential sources/loads to minimize susceptiblity to 
interference, which is usually common-mode and thus will be rejected by a 
differential circuit.  This costs chip area and circuit complexity.
7.  Use logic which detects *currents* rather than voltages.  Since 
interference usually induces voltage, this sort of logic will reject 
interference.  The cost is increased power and chip complexity.

These are just a few of the techniques and you can see that they all have 
their drawbacks as well as advantages.  Go into the IEEE database, do a 
search on "high speed design", and you'll be amazed at what comes out.
GOOD LUCK!